This invention generally relates to microprocessors, and more specifically to improvements in cache memory access circuits, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a cache with an array of data lines with an associated array of tags. Data is loaded into various of lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, a qualifier value is stored in a qualifier field in the tag. The qualifier value specifies a usage characteristic of data stored in an associated data line of the cache. In response to an operation command, each tag in the array of tags that contains a specified qualifier value is modified in accordance with the operation command. Various types of operation commands can be included in an embodiment of the invention, such as clean, flush, clean-flush, lock, and unlock, for example.
The qualifier field in the present embodiment represents a task-ID indicative of a software task that requested the associated data. There is a second qualifier field that represents a resource-ID indicative of a hardware resource that requested the data.
In another embodiment, there may be other qualifiers, such as a qualifier field that indicates the data is shared, for example.
In another embodiment, separate valid bits are associated with the address field and the qualifier field of the tag. If a qualifier field valid bit is not set, then the qualifier field is ignored.
In another embodiment, a digital system is provided with a cache that has a data array with a plurality of lines for holding data and a tag array having a plurality of lines for holding a plurality of tags. Each line of the tag array is associated with a particular line of the data array and each line of the tag array contains an address field and a qualifier field. Control circuitry is arranged to select a tag and then examine the qualifier field of the selected tag. The control circuitry can than modify the tag in response to an operation command, such as clean, flush, clean-flush, lock, and unlock, for example. The control circuitry receives a specified qualifier value from a given operation command and only modifies tags in which the qualifier field matches the specified qualifier value.
The cache is a level two cache, but in other embodiments the cache may be a first level or a higher level cache. In another embodiment, there are additional qualifier fields and additional comparison circuitry to compare the additional qualifier field(s) to specified qualifier values.
In another embodiment, a first level cache embodying the present invention may make requests to a second level cache that also embodies the present invention.